1. Field of the Invention
The present invention generally relates to a dot clock generator for a liquid crystal display device, and more particularly to such generator which can generate a dot clock with less skew from a sync signal.
2. Related Art
The CRT (cathode ray tube) has been widely used as a monitor of a personal computer, and the interface between the personal computer and CRT is made unique to the CRT. Specifically, R, G, and B analog signals, and vertical and horizontal sync signals are generated in the personal computer unit and provided to the CRT. When a liquid crystal display device is used instead of a CRT in a computer system employing such interface, the liquid crystal display device needs to generate an additional dot clock. In other words, the liquid crystal display device needs to receive R, G, and B digital signals for every dot timing (dot clock) to drive the liquid crystal panel based on these signals. Since the personal computer unit outputs only the analog RGB and sync signals to the above CRT interface, it is necessary to generate a dot clock from the sync signals and, according to the timing of this clock, convert the analog RGB signals to digital RGB signals by the A/D conversion.
A phase locked loop (PLL) circuit shown in FIG. 1 may be used to generate a dot clock from a sync signal, i.e. horizontal sync signal. In FIG. 1, phase comparator 11 is supplied with the horizontal sync signal and the output of frequency divider 12. The comparison outputs (positive and negative) of phase comparator 11 is inputted to voltage controlled oscillator (VCO) 15 via filter 13 and capacitor 14. Then the output of VCO 15 is given as a dot clock and fed back to frequency divider 12. Assuming that frequency divider 12 has a division ratio of 1/N, the dot clock to be outputted will have a frequency of N times the horizontal sync signal.
In the above conventional arrangement, however, a problem arises that the screen is disturbed by the jitters of the dot clock due to the jitters of the horizontal sync signal itself, the beat between the jitters of the horizontal sync signal, and the circulation of power supply noise into VCO 15.
In addition, with such arrangement, the noise from frequency divider 12 is superimposed on the voltage across capacitor 14, leading to a difficulty in generating a stable dot clock necessary for the liquid crystal display. If the phase of frequency divider 12 is delayed with respect to the horizontal sync signal, i.e. if the clock frequency is too low, the voltage across capacitor 14 would increase to increase the clock frequency for compensation, as shown in FIG. 2A. On the other hand, if the phase of frequency divider 12 is advanced with respect to the horizontal sync signal, i.e. if the clock frequency is too high, the voltage across capacitor 14 would decrease to lower the clock frequency for compensation, as shown in FIG. 2B. However, the voltage across capacitor 14 is subject to the noise from frequency divider 12 which skews the clock frequency to thereby disturb the screen.